larpix package¶
larpix.larpix module¶
A module to control the LArPix chip.
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class
larpix.larpix.
Chip
(chip_id, io_chain)[source]¶ Bases:
object
Represents one LArPix chip and helps with configuration and packet generation.
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export_reads
(only_new_reads=True)[source]¶ Return a dict of the packets this Chip has received.
If
only_new_reads
isTrue
(default), then only the packets since the last time this method was called will be in the dict. Otherwise, all of the packets stored inself.reads
will be in the dict.
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num_channels
= 32¶
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class
larpix.larpix.
Configuration
[source]¶ Bases:
object
Represents the desired configuration state of a LArPix chip.
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TEST_FIFO
= 2¶
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TEST_OFF
= 0¶
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TEST_UART
= 1¶
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adc_burst_length
¶
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adc_burst_length_address
= 51¶
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channel_mask
¶
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channel_mask_addresses
= [52, 53, 54, 55]¶
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compare
(config)[source]¶ Returns a dict containing pairs of each differently valued register Pair order is (self, other)
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cross_trigger_mode
¶
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csa_bypass
¶
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csa_bypass_select
¶
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csa_bypass_select_addresses
= [34, 35, 36, 37]¶
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csa_gain
¶
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csa_gain_and_bypasses_address
= 33¶
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csa_monitor_select
¶
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csa_monitor_select_addresses
= [38, 39, 40, 41]¶
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csa_testpulse_dac_amplitude
¶
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csa_testpulse_dac_amplitude_address
= 46¶
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csa_testpulse_enable
¶
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csa_testpulse_enable_addresses
= [42, 43, 44, 45]¶
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external_trigger_mask
¶
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external_trigger_mask_addresses
= [56, 57, 58, 59]¶
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fifo_diagnostic
¶
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fpga_packet_size
= 10¶
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from_dict_registers
(d)[source]¶ Load in the configuration specified by a dict of (register, value) pairs.
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global_threshold
¶
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global_threshold_address
= 32¶
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internal_bypass
¶
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num_registers
= 63¶
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periodic_reset
¶
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pixel_trim_threshold_addresses
= [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]¶
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pixel_trim_thresholds
¶
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register_names
= ['pixel_trim_thresholds', 'global_threshold', 'csa_gain', 'csa_bypass', 'internal_bypass', 'csa_bypass_select', 'csa_monitor_select', 'csa_testpulse_enable', 'csa_testpulse_dac_amplitude', 'test_mode', 'cross_trigger_mode', 'periodic_reset', 'fifo_diagnostic', 'sample_cycles', 'test_burst_length', 'adc_burst_length', 'channel_mask', 'external_trigger_mask', 'reset_cycles']¶
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reset_cycles
¶
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reset_cycles_addresses
= [60, 61, 62]¶
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sample_cycles
¶
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sample_cycles_address
= 48¶
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test_burst_length
¶
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test_burst_length_addresses
= [49, 50]¶
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test_mode
¶
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test_mode_xtrig_reset_diag_address
= 47¶
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class
larpix.larpix.
Controller
(port=None, timeout=1)[source]¶ Bases:
object
Controls a collection of LArPix Chip objects.
Properties and attributes:
chips
: theChip
objects that the controller controlsall_chip
: all possibleChip
objects (considering there are a finite number of chip IDs), initialized on object constructionport
: the path to the serial port, i.e. “/dev/(whatever)” (default:None
[will attempt to auto-find correct port])timeout
: the timeout used for serial commands, in seconds. This can be changed between calls to the read and write commands. (default:1
)reads
: list of all the PacketCollections that have been sent back to this controller. PacketCollections are created byrun
,write_configuration
, andread_configuration
, but not by any of theserial_*
methods.use_all_chips
: ifTrue
, look up chip objects inself.all_chips
, else look up inself.chips
(default:False
)
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disable
(chip_id=None, channel_list=range(0, 32), io_chain=0)[source]¶ Update channel mask to disable specified chips/channels. If none specified, disable all chips/channels
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disable_analog_monitor
(chip_id=None, channel=None, io_chain=0)[source]¶ Disable the analog monitor for a specified chip and channel, if none are specified disable the analog monitor for all chips in self.chips and all channels
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disable_testpulse
(chip_id=None, channel_list=range(0, 32), io_chain=0)[source]¶ Disable testpulser for specified chip/channels. If none specified, disable for all chips/channels
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enable
(chip_id=None, channel_list=range(0, 32), io_chain=0)[source]¶ Update channel mask to enable specified chips/channels. If none specified, enable all chips/channels
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enable_analog_monitor
(chip_id, channel, io_chain=0)[source]¶ Enable the analog monitor on a single channel on the specified chip. Note: If monitoring a different chip, call disable_analog_monitor first to ensure that the monitor to that chip is disconnected.
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enable_testpulse
(chip_id, channel_list, io_chain=0, start_dac=255)[source]¶ Prepare chip for pulsing - enable testpulser and set a starting dac value for specified chip/channel
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issue_testpulse
(chip_id, pulse_dac, min_dac=0, io_chain=0)[source]¶ Reduce the testpulser dac by pulse_dac and write_read to chip for 0.1s
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load
(filename)[source]¶ Load the data in filename into the controller.
Overwrites all data inside the controller!
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multi_read_configuration
(chip_reg_pairs, timeout=1, message=None)[source]¶ Send multiple read configuration commands at once.
chip_reg_pairs
should be a list/iterable whose elements are Chip objects (to read entire configuration) or (chip, registers) tuples to read only the specified register(s). Registers could beNone
(i.e. all), anint
for that register only, or an iterable of ``int``s.Examples:
These first 2 are equivalent and read the full configurations
>>> controller.multi_read_configuration([chip1, chip2, ...]) >>> controller.multi_read_configuration([(chip1, None), chip2, ...])
These 2 read the specified registers for the specified chips in the specified order
>>> controller.multi_read_configuration([(chip1, 1), (chip2, 2), ...]) >>> controller.multi_read_configuration([(chip1, range(10)), chip2, ...])
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multi_write_configuration
(chip_reg_pairs, write_read=0, message=None)[source]¶ Send multiple write configuration commands at once.
chip_reg_pairs
should be a list/iterable whose elements are an valid arguments toController.write_configuration
, excluding thewrite_read
argument. Just like in the singleController.write_configuration
, settingwrite_read > 0
will have the controller read data during and after it writes, for however many seconds are specified.Examples:
These first 2 are equivalent and write the full configurations
>>> controller.multi_write_configuration([chip1, chip2, ...]) >>> controller.multi_write_configuration([(chip1, None), chip2, ...])
These 2 write the specified registers for the specified chips in the specified order
>>> controller.multi_write_configuration([(chip1, 1), (chip2, 2), ...]) >>> controller.multi_write_configuration([(chip1, range(10)), chip2, ...])
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read_channel_pedestal
(chip_id, channel, io_chain=0, run_time=0.1)[source]¶ Set channel threshold to 0 and report back on the recieved adcs from channel Returns mean, rms, and packet collection
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sort_packets
(collection)[source]¶ Sort the packets in
collection
into each chip inself.all_chips
(ifself.use_all_chips
) orself.chips
(otherwise).
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start_byte
= b's'¶
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stop_byte
= b'q'¶
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verify_configuration
(chip_id=None, io_chain=0)[source]¶ Read chip configuration from specified chip and return a bool that is True if the read chip configuration matches the current configuration stored in chip instance Also returns a dict containing the values of registers that are different (read register, stored register)
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class
larpix.larpix.
Packet
(bytestream=None)[source]¶ Bases:
object
A single 54-bit LArPix UART data packet.
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CONFIG_READ_PACKET
= bitarray('11')¶
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CONFIG_WRITE_PACKET
= bitarray('10')¶
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DATA_PACKET
= bitarray('00')¶
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TEST_PACKET
= bitarray('01')¶
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channel_id
¶
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channel_id_bits
= slice(37, 44, None)¶
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chipid
¶
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chipid_bits
= slice(44, 52, None)¶
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config_unused_bits
= slice(1, 28, None)¶
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dataword
¶
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dataword_bits
= slice(3, 13, None)¶
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fifo_full_bit
= 1¶
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fifo_full_flag
¶
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fifo_half_bit
= 2¶
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fifo_half_flag
¶
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num_bytes
= 7¶
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packet_type
¶
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packet_type_bits
= slice(52, 54, None)¶
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parity_bit
= 0¶
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parity_bit_value
¶
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parity_calc_bits
= slice(1, 54, None)¶
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register_address
¶
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register_address_bits
= slice(36, 44, None)¶
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register_data
¶
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register_data_bits
= slice(28, 36, None)¶
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size
= 54¶
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test_counter
¶
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test_counter_bits_11_0
= slice(1, 13, None)¶
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test_counter_bits_15_12
= slice(40, 44, None)¶
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timestamp
¶
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timestamp_bits
= slice(13, 37, None)¶
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class
larpix.larpix.
PacketCollection
(packets, bytestream=None, message='', read_id=None, skipped=None)[source]¶ Bases:
object
Represents a group of packets that were sent to or received from LArPix.
Index into the PacketCollection as if it were a list:
>>> collection[0] Packet(b' ') >>> first_ten = collection[:10] >>> len(first_ten) 10 >>> type(first_ten) larpix.larpix.PacketCollection >>> first_ten.message 'my packets | subset slice(None, 10, None)'
To view the bits representation, add ‘bits’ to the index:
>>> collection[0, 'bits'] '00000000 00000000 00000000 00000000 00000000 00000000 000111' >>> bits_format_first_10 = collection[:10, 'bits'] >>> type(bits_format_first_10[0]) str
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extract
(attr, **selection)[source]¶ Extract the given attribute from packets specified by selection and return a list.
Any key used in Packet.export is a valid attribute or selection:
- all packets:
- bits
- type (data, test, config read, config write)
- chipid
- parity
- valid_parity
- data packets:
- channel
- timestamp
- adc_count
- fifo_half
- fifo_full
- test packets:
- counter
- config packets:
- register
- value
Usage:
>>> # Return a list of adc counts from any data packets >>> adc_data = collection.extract('adc_counts') >>> # Return a list of timestamps from chip 2 data >>> timestamps = collection.extract('timestamp', chipid=2) >>> # Return the most recently read global threshold from chip 5 >>> threshold = collection.extract('value', register=32, type='config read', chip=5)[-1]
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