LArPix v1 ASIC Configuration Registers¶
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Configuration.
register_names
= ['pixel_trim_dac', 'threshold_global', 'csa_gain', 'csa_bypass_enable', 'bypass_caps_en', 'csa_enable', 'ibias_tdac', 'ibias_comp', 'ibias_buffer', 'ibias_csa', 'ibias_vref_buffer', 'ibias_vcm_buffer', 'ibias_tpulse', 'ref_current_trim', 'override_ref', 'ref_kickstart', 'vref_dac', 'vcm_dac', 'csa_bypass_select', 'csa_monitor_select', 'csa_testpulse_enable', 'csa_testpulse_dac', 'current_monitor_bank0', 'current_monitor_bank1', 'current_monitor_bank2', 'current_monitor_bank3', 'voltage_monitor_bank0', 'voltage_monitor_bank1', 'voltage_monitor_bank2', 'voltage_monitor_bank3', 'voltage_monitor_refgen', 'digital_monitor_enable', 'digital_monitor_select', 'digital_monitor_chan', 'slope_control0', 'slope_control1', 'slope_control2', 'slope_control3', 'chip_id', 'load_config_defaults', 'enable_fifo_diagnostics', 'clk_ctrl', 'enable_miso_upstream', 'enable_miso_downstream', 'enable_miso_differential', 'enable_mosi', 'test_mode_uart0', 'test_mode_uart1', 'test_mode_uart2', 'test_mode_uart3', 'enable_cross_trigger', 'enable_periodic_reset', 'enable_rolling_periodic_reset', 'enable_periodic_trigger', 'enable_rolling_periodic_trigger', 'enable_periodic_trigger_veto', 'enable_hit_veto', 'adc_hold_delay', 'adc_burst_length', 'channel_mask', 'external_trigger_mask', 'cross_trigger_mask', 'periodic_trigger_mask', 'periodic_reset_cycles', 'periodic_trigger_cycles', 'enable_dynamic_reset', 'enable_min_delta_adc', 'threshold_polarity', 'reset_length', 'mark_first_packet', 'reset_threshold', 'min_delta_adc', 'digital_threshold']¶
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class
larpix.configuration.configuration_v1.
Configuration_v1
[source]¶ Represents the desired configuration state of a LArPix v1 chip.
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register_names
= ['pixel_trim_thresholds', 'global_threshold', 'csa_gain', 'csa_bypass', 'internal_bypass', 'csa_bypass_select', 'csa_monitor_select', 'csa_testpulse_enable', 'csa_testpulse_dac_amplitude', 'test_mode', 'cross_trigger_mode', 'periodic_reset', 'fifo_diagnostic', 'sample_cycles', 'test_burst_length', 'adc_burst_length', 'channel_mask', 'external_trigger_mask', 'reset_cycles']¶ This attribute lists the names of all available configuration registers. Each register name is available as its own attribute for inspecting and setting the value of the corresponding register.
Certain configuration values are set channel-by-channel. These are represented by a list of values. For example:
>>> conf.pixel_trim_thresholds[2:5] [16, 16, 16] >>> conf.channel_mask[20] = 1 >>> conf.external_trigger_mask = [0] * 32
Additionally, other configuration values take up more than or less than one complete register. These are still set by referencing the appropriate name. For example,
cross_trigger_mode
shares a register with a few other values, and adjusting the value of thecross_trigger_mode
attribute will leave the other values unchanged.
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enable_channels
(list_of_channels=None)[source]¶ Shortcut for changing the channel mask for the given channels to “enable” (i.e. 0).
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disable_channels
(list_of_channels=None)[source]¶ Shortcut for changing the channel mask for the given channels to “disable” (i.e. 1).
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enable_external_trigger
(list_of_channels=None)[source]¶ Shortcut for enabling the external trigger functionality for the given channels. (I.e. disabling the mask.)
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disable_external_trigger
(list_of_channels=None)[source]¶ Shortcut for disabling the external trigger functionality for the given channels. (I.e. enabling the mask.)
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enable_testpulse
(list_of_channels=None)[source]¶ Shortcut for enabling the test pulser for the given channels.
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disable_testpulse
(list_of_channels=None)[source]¶ Shortcut for disabling the test pulser for the given channels.
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